The invention pertains generally to the field of power conversion, and more particularly to digitally-controlled switched-mode DC/DC converters.
A broad class of switched-mode DC/DC power converters exists with the property that the ratio of the average output voltage to the input voltage is determined by the average duty cycle of a controllable switching device within the power conversion stage of the converter. Examples include buck, boost, inverting buck-boost, forward, and flyback converters, operated in the continuous conduction mode (CCM). Where the input voltage (line) or the output current (load) or both vary slowly, or there is a requirement to track abrupt changes in load with minimal output voltage error, regulation of these converters is accomplished by continually estimating the output voltage error (the output voltage error being the difference between the uncorrupted output voltage and the desired output voltage) and continually adjusting the duty cycle of the switching device to compensate for changes in load conditions manifest in output voltage error estimates. In this case, the act of regulation consists of controlling, cycle by cycle, the duty cycle of the switching device in accordance with output voltage error estimates, so that the amplitude of the output voltage error is continually minimized.
Regulation mechanisms for this purpose, known as PWM regulators, generally incorporate a pulse width control mechanism and a duty cycle control mechanism, where the former generates the ON pulse appropriate to the realization of the duty cycle generated by the latter. Accordingly, the goal of the duty cycle control mechanism is to estimate the target duty cycle (the target duty cycle being the duty cycle essential to achieve the desired output voltage). A duty cycle control mechanism is commonly a feedback mechanism, driven by the output voltage error, but it could as well be a feedforward mechanism, driven by the input voltage, or it could be some combination of the two.
The most commonly used pulse width control mechanisms are analog in nature; that is they accept as input a continuously variable analog signal representing the desired duty cycle, and they output pulses of continuously variable width. As in other previously analog fields, continuous advances in integrated circuit technology have stimulated the application of digital techniques to the field of power conversion. As a result, the first digital PWM control mechanisms, replacing analog PWM control mechanisms, have been developed and are being applied together with digital duty cycle control mechanisms, to realize digital implementations of familiar analog PWM regulators. Digital PWM control mechanisms are generally implemented using a counter and a comparator or a multistage ring oscillator. In the case of the former, a faster clock (for improved temporal resolution) implies higher power dissipation, impacting efficiency. In case of the latter, more ring oscillator stages (for improved temporal resolution) implies more silicon area, impacting manufacturing cost.
Whether counter-comparator or multistage-ring-oscillator, it is the nature of digital PWM regulation mechanisms that the generated pulse widths (and consequently, the commanded duty cycles) are quantized—a consequence of the temporal resolution of the digital PWM control mechanism. If the temporal resolution of the PWM control mechanism is Δt, then the pulse widths are constrained to be integral multiples of Δt. For the purposes herein, we shall assume that switching cycles, spanning consecutive ON and OFF pulses, are likewise constrained to be integral multiples of Δt.
One challenge to those who would apply digital PWM regulation mechanisms to power converters, especially DC/DC converters employed in battery-powered mobile applications, is the challenge of achieving acceptable application performance with digital regulation mechanisms. Quantization of pulse widths translates into quantized duty cycles, which constrain the ability of any duty cycle control mechanism to limit output voltage error to an arbitrary application-dictated level.
To understand the nature of this challenge, consider a DC/DC converter in a battery powered mobile application. The switching frequency is typically set in the neighborhood of 1 MHz, to minimize the size and cost of discrete components and maximize the operating efficiency of the converter. Assuming a fixed switching frequency of 1 MHz, a digital PWM regulation mechanism operating at 16 MHz would thus be able to generate pulses widths of 0, 1/16 usec, 2/16 usec, 3/16 usec . . . 16/16 usec, translating to just 17 instantaneous duty cycles (including 0 and 1) available to the duty cycle control mechanism. To maintain the desired output voltage over a range of line and load conditions, the regulator must sequence a pair of these quantized duty cycles, one smaller than the target duty cycle, and the other larger, applying the converter's output filter to achieve a time-averaged duty cycle equal to the target duty cycle.
In one embodiment of this concept (cf. U.S. Pat. No. 5,272,614), the duty cycle control mechanism incorporates coarse and fine quantizers to effect the time averaging while the subsequent duty cycle is being computed. In another embodiment of this concept (cf. U.S. Pat. No. 6,677,733), the duty cycle control mechanism examines the output voltage error estimate within each switching cycle, and if it is positive, selects the smaller duty cycle for the next cycle of the switching device. Similarly, if the current output voltage error estimate is negative, it selects the larger duty cycle for the next cycle of the switching device. While simple and effective, this duty cycle control mechanism is limited (by the resolution of the available duty cycles) in its ability to regulate within acceptable levels of output voltage error.
To achieve acceptable levels of output voltage error, the elimination of steady-state limit cycles, characteristic of digital PWM regulated converters is generally necessary. In a paper entitled “Quantization Resolution and Limit Cycling in Digitally Controlled PWM Converters”, published in the January, 2003, issue of IEEE Transactions on Power Electronics, authors Peterchev and Sanders describe the limit cycling behavior of digitally regulated, fixed frequency buck converters and enumerate a number of conditions necessary to prevent such behavior. The paper also describes the incorporation of digital dither within the duty cycle control mechanism to improve the effective resolution of the digital PWM control mechanism, applying the switching pattern approach described in U.S. Pat. No. 5,886,513, to closed loop control.
The authors noted that to achieve a regulation resolution (error) of the order of 10 mv, with an input voltage of the order of 5 volts, 10 bits of digital PWM resolution is required, implying a 1 GHz clock (in a counter-comparator implementation) or 1024 stages (in a multistage ring oscillator implementation) assuming a switching frequency of 1 MHz. On a more optimistic note, the authors presented experimental results demonstrating the application of digital dither to reduce the requisite digital PWM resolution from 10 bits to 7 bits in regulating a 4-phase buck converter. While the power dissipation associated with a 128 MHz clock may be acceptable in multiphase applications, the world of battery-powered mobile applications is another story. In mobile applications, the requirement for clock frequencies of the order of 128 MHz (or for expensive multistage ring oscillators) will delay if not preclude the adoption of digital PWM regulators.
Clearly there is a need for digital control methods that mitigate the requirement for higher clock frequencies or higher-cost controller implementations solely for the purpose of achieving acceptable output voltage error in a broad class of DC/DC converters.